1. Field of the Invention
Example embodiments of the present invention relate to semiconductor memory devices, for example, non-volatile memory devices having a floating node and/or a trap-type node as a storage node, and methods of fabricating the same.
2. Description of the Related Art
Related art flash memory devices have a floating node such as a polysilicon film as a storage node. Related art silicon-oxide-nitride-oxide-silicon (SONOS) memory devices have a trap-type node such as silicon nitride film as a storage node. In a related art non-volatile memory device, limited memory integration and/or speed may result from limitations in forming fine patterns.
A related art Fin-FET may use top and side surfaces of a fin structure as a channel region. Therefore, the Fin-FET may have a larger channel area as compared to a planar transistor, which may result in a higher current flow. As a result, the Fin-FET may provide higher performance than the planar transistor.
However, because related art Fin-FETs are fabricated using a silicon-on-insulator (SOI) substrate, the fin is floated from the body of the substrate making it more difficult to control the threshold voltage of the transistor using a body-bias. As a result, it may be more difficult to control the threshold voltage of a complementary metal-oxide-semiconductor (CMOS) transistor. Furthermore, because the related art fin memory cell uses an area of at least 2 F×2 F to provide 2-bit operation when the gate length is 1 F, the area per bit is 2 F2/bit. An area per bit of 2 F2/bit may limit the performance of the fin memory cell.